What is static timing analysis?
STA is a method for checking timing relationships through a digital circuit. The tool builds a timing graph from the netlist, cell timing models, interconnect estimates or extracted parasitics, and clock and I/O constraints. It propagates earliest and latest arrival times along paths, calculates required times at endpoints, and reports margins called slack.
It is called static because it does not simulate one particular sequence of signal values. The analysis considers modeled timing arcs and path relationships without requiring a test vector to activate each path. This lets engineers check large designs and many timing scenarios efficiently. STA still depends on correct inputs: missing clocks, wrong exceptions, unrealistic delays or inconsistent operating conditions can make a report misleading.
Static analysis and dynamic simulation
Functional simulation answers questions about behaviour for applied stimulus: does a protocol transaction complete, does reset work, or does a state machine produce the expected sequence? STA answers whether constrained paths can satisfy timing across modeled conditions. A simulation may not exercise every path or corner case, and it may use timing models that are insufficient for signoff. STA does not establish that the logic implements the intended function. Good design closure uses both, together with formal, lint, CDC/RDC and physical checks as appropriate.
Timing paths: startpoints and endpoints
A path begins at a timing startpoint and ends at an endpoint. Common path groups include register-to-register, input-to-register, register-to-output and input-to-output. For a register-to-register setup path, data launches from a source register after a clock edge, propagates through combinational cells and wires, and must arrive at the destination register before its next active edge. A hold check examines the earliest data relative to the same relevant capture edge.
The launch clock reaches the source register; the capture clock reaches the destination. Their arrival difference is skew. Clock latency is the travel time from a clock source to a register, and it may be idealized early in a flow then propagated after clock-tree implementation. Uncertainty accounts for selected margins such as jitter and modeling effects. The precise relationship depends on generated clocks, phase, frequency, edge polarity and path type.
Cell and net delays depend on input transition (slew), output load or capacitance, process, voltage and temperature. A slow transition can change the delay of a receiving cell; a large load can increase the time needed for a net to switch. Physical implementation changes wire lengths and parasitics, so timing evolves as a design is placed and routed.
Timing constraints and SDC
Design Constraint (SDC) is a commonly used Tcl-based format for describing clocks and timing assumptions to EDA tools. Constraints can define clock periods and waveforms, generated clocks, clock uncertainty, input and output delays, transition limits, loads and exceptions. Input delay models when external data may arrive relative to a reference clock; output delay describes the timing requirement at an interface endpoint relative to an external capture relationship.
A false-path exception says a path need not satisfy a particular timing relationship because that relationship is functionally impossible or irrelevant under a carefully justified design assumption. It must not be used to hide a difficult path. A multicycle path changes the number of clock cycles allowed for a transfer when the architecture truly defines that behaviour. Such constraints need corresponding setup and hold treatment and design review.
Constraints are part of the design specification. An unconstrained path has no meaningful guarantee from the report simply because no violation is printed. Conversely, over-constraining paths can create impossible goals and waste implementation effort. Review coverage, generated clocks, asynchronous clock groups, I/O timing and exception rationale with the design.
Required arrival time, actual arrival time and slack
Arrival time is when data is calculated to reach a point along the path. Required time is the latest acceptable arrival for setup, or a related earliest acceptable boundary for hold. Setup slack is commonly expressed as required time minus arrival time. Positive slack means the analyzed path meets that check with margin; negative slack indicates the path misses its requirement by that amount. Hold slack conventions also compare available and required timing, but report sign and labels should be read according to the tool’s report format.
Consider a simplified setup path with a required arrival of 1.00 ns and a calculated latest arrival of 0.92 ns. Setup slack is 1.00 − 0.92 = +0.08 ns, or +80 ps. If the arrival were 1.04 ns, the slack would be −0.04 ns (−40 ps), a setup violation. These numbers are illustrative; the report’s reference edge, uncertainty, skew, delays and derates determine the actual calculation.
For a path view, trace the launch clock path, launch register clock-to-Q, each cell and net, the capture endpoint setup requirement, capture clock path, uncertainty and final slack. Do not focus only on the total. The worst cell, high-fanout net, poor slew or unexpected clock relationship may suggest the right investigation. The companion guide explains setup and hold timing in more detail.
PVT corners and on-chip variation
Process, voltage and temperature (PVT) affect device and interconnect behaviour. Process models represent manufacturing variation within characterized conditions; voltage affects transistor drive; temperature influences device and wire properties. A design is checked across selected corners and modes because a path that is fast in one condition may be slow in another. Setup commonly cares about slow data conditions and hold about fast data conditions, although clock paths and library characterization make the actual corner setup more nuanced.
On-chip variation models differences across locations and paths on the same die. Derating, statistical techniques or advanced variation models may account for some of these effects. Clock reconvergence pessimism removal (CRPR) can remove overly pessimistic treatment of shared clock segments in supported analyses. These methods refine the model; they do not eliminate the need to understand the assumptions and signoff methodology.
Pre-layout analysis uses early estimates for interconnect and clock structure. Post-placement and post-route analysis uses progressively more physical information, including extracted parasitics. Routing can add capacitance, coupling and resistance, so a path that passes before routing may fail after extraction. Signal integrity analysis can evaluate aggressor effects and noise when required by the process and design methodology.
Timing reports and common review questions
A timing report identifies the startpoint and endpoint, path group, launch and capture clocks, path type, cell and net arcs, arrival time, required time and slack. Review whether the intended clock is used, the path is constrained, the endpoint is correct, and the report corresponds to the relevant mode and corner. Look for negative slack, large transition or capacitance warnings, unexpected exceptions, and differences between early and extracted parasitics.
STA and simulation complement one another. A testbench can show functional correctness for explored transactions but does not prove every path meets timing. STA can check timing on modeled paths but does not show that a protocol or algorithm is correct. Formal methods can prove selected properties or equivalence under assumptions; physical verification checks geometric and manufacturing rules. Each answers a different question within the ASIC design flow.
Begin with the Semiconductor & VLSI hub, review the VLSI Design Hub, and compare programmable and custom implementations in ASIC vs FPGA.