ASIC Design Flow: From RTL to GDSII

The high-level ASIC flow

The diagram groups work by its main emphasis. In a real project, verification, timing and power analysis continue across several stages, and individual organisations define their own signoff checklists.

Several steps can repeat: a timing or congestion issue may lead to placement changes, a logic update, or an architectural decision. A corrected RTL revision generally needs renewed verification and implementation checks.

Front-end design: requirements through RTL

1. Specification

The specification states what the product must do and the conditions under which it must do it. It defines interfaces, data rates, reset behaviour, clock domains, power targets, security assumptions, test needs and operating environment. Unclear requirements become expensive later because every team may interpret the behaviour differently. Measurable acceptance criteria and explicit assumptions help design and verification share the same target.

2. Architecture

Architects partition the system into blocks and decide how processing, memory, control and interfaces fit together. They consider bandwidth, latency, parallelism, area, power and reuse. A system may use embedded processors, fixed-function logic, memories, analog interfaces or accelerators. Architectural trade-offs constrain later RTL and floorplanning, so early estimates should be revisited when implementation evidence arrives.

3. RTL design

Register-transfer-level code describes state transitions and combinational functions between registers. Designers define module boundaries, reset strategy, clocking, arbitration, pipelines and protocol behaviour. Synthesizable RTL must express hardware the target tool understands. Coding style, naming, parameter choices and clear assumptions help review and reuse. The companion article compares Verilog and SystemVerilog.

4. Functional verification

Verification compares design behaviour against the specification through directed tests, constrained-random scenarios, assertions, scoreboards and coverage. Test plans identify normal operation, boundary conditions, reset sequences, concurrency and error handling. Coverage can expose untested scenarios but is not itself proof that the design is correct. Formal methods can prove selected properties or equivalence under stated assumptions, complementing simulation.

5. Lint and CDC/RDC

Lint checks source for suspicious constructs, width mismatches, unused signals, unintended latches and style issues. Clock-domain crossing (CDC) analysis identifies signals transferred between unrelated or differently timed clocks, where metastability and coherency need deliberate handling. Reset-domain crossing (RDC) checks interactions among reset domains and deassertion behaviour. These analyses identify structural risks; waivers need clear technical justification and review.

Synthesis and physical design

6. Logic synthesis

Synthesis transforms RTL into a gate-level netlist built from cells in a technology library. It uses constraints such as clocks and I/O timing to optimise logic for timing, area and power goals. The netlist is an implementation representation, not the final layout. Equivalence checking may compare the synthesized design against RTL to establish that transformations preserve intended logic under the defined setup.

7. Design for test and equivalence

Design-for-test (DFT) adds structures such as scan chains and built-in self-test to make internal states more controllable and observable during manufacturing test. Memory test and boundary-scan needs may also be included. Formal equivalence can check that transformations—such as synthesis or engineering changes—preserve behaviour relative to a reference. These are distinct questions: DFT supports defect detection in manufactured parts, while equivalence checks logic correspondence.

8. Floorplanning and power planning

Floorplanning assigns approximate locations and dimensions to major blocks, memories, interfaces and other physical resources. It establishes pin placement, routing channels and initial density assumptions. Power planning creates a network that distributes supply and return currents across the die. Poor floorplanning can create long wires, congestion or difficult power delivery, so early placement and timing feedback may cause repeated refinement.

9. Placement

Placement assigns standard cells to physical locations. Tools balance timing, congestion, density, power and design rules while respecting fixed or hierarchical regions. Placement affects wire length and load; a logically short path may become physically long if its cells are far apart. Timing-driven placement uses path information, but estimates become more accurate as clocks and parasitics are refined.

10. Clock Tree Synthesis

Clock tree synthesis (CTS) builds a distribution network that delivers clock edges to sequential elements. It inserts buffers and balances path delays to control skew and transition. The resulting clock network consumes area and power and interacts with both setup and hold timing. Clock-tree quality depends on constraints, placement, clock-gating structure and physical implementation rules.

11. Routing

Routing connects cell pins and block interfaces through metal layers while observing spacing, width, via and congestion rules. Global routing estimates paths; detailed routing assigns exact geometries and vias. Routing changes resistance and capacitance and can create coupling between neighbouring nets. Parasitic extraction feeds these physical effects into timing and signal-integrity analysis.

Timing, physical verification and signoff

12. Static timing analysis

STA checks setup and hold relationships across constrained timing paths and selected modes and corners. It reports arrival times, required times and slack. Engineers review clocks, exceptions, input/output delays, uncertainty and path detail. Read ASARK’s static timing analysis guide and setup versus hold explanation for the core timing concepts.

13. Signal integrity and power integrity

Signal-integrity analysis studies effects such as crosstalk, noise and interconnect coupling where relevant. Power-integrity analysis evaluates voltage drop across the supply network, often called IR drop, and considers current demand and reliability. Electromigration checks assess whether sustained current density could damage interconnect over the intended lifetime. These analyses depend on activity assumptions, extraction and process-specific methodology.

14. Physical verification: DRC and LVS

Design-rule checking (DRC) tests layout geometry against manufacturing rules such as spacing, width and enclosure. Layout-versus-schematic (LVS) compares the connectivity extracted from layout with the intended schematic or netlist. Passing DRC does not prove functional correctness; passing LVS does not by itself prove timing or reliability. Other checks can include antenna rules, density, latch-up and electrical rule verification, depending on the process.

15. Engineering change orders

An engineering change order (ECO) is a controlled update made late in the design process. A change may repair functionality, improve timing, address a physical rule or update test logic. ECOs need traceability and revalidation: a small gate-level edit can affect equivalence, timing, routing and physical checks. The team must confirm the final database corresponds to the reviewed sources and constraints.

16. Signoff and GDSII tape-out

Signoff is the agreed set of checks and reviews that establish readiness for manufacturing handoff. It can cover STA, power integrity, physical verification, DFT, formal equivalence, reliability and data integrity. Exact criteria vary by product and foundry process. GDSII (or another accepted layout exchange format) represents the final mask geometry supplied for fabrication. Tape-out is the release of that database and associated information to the manufacturing flow, not the moment a chip is already proven in a system.

Fabrication, packaging and test

17. Fabrication

The foundry processes wafers through repeated material deposition, patterning, etching, doping and other operations to form devices and interconnects. Each process has design rules and variability models that informed implementation. Wafer fabrication takes place across many layers; manufacturing results are then assessed through process control and electrical testing.

18. Packaging

After wafer processing and initial test, dies are separated and assembled into packages. The package provides electrical connections, mechanical protection and heat paths. Some products use multiple dies or stacked memory. Package and board characteristics affect power, thermal behaviour and signal integrity, so system assumptions should be considered before finalizing a chip.

19. Test and product validation

Manufacturing test screens parts using test patterns and production limits. DFT structures help observe and control internal logic; memory BIST can exercise arrays. Product validation then checks chips in representative systems, including firmware, boards, thermal conditions and interfaces. Silicon behaviour may reveal issues that require characterization, a firmware workaround or a later design revision. Test yield and reliability are measured by the responsible manufacturing and product teams; this article makes no numeric yield claim.

Front end, back end and signoff at a glance

The labels are useful shorthand, not rigid ownership boundaries. Verification starts early and continues late; synthesis bridges RTL and implementation; signoff findings can send work back to design or physical implementation. Good change control preserves the connection between requirements, source, netlist, layout and delivered silicon.

For broader foundations, return to ASARK’s Semiconductor & VLSI hub and What is VLSI?. Compare implementation choices in ASIC vs FPGA.