Semiconductor · Timing Fundamentals

Setup Time vs Hold Time: Timing Violations Explained

Registers do not capture data instantaneously at an ideal mathematical edge. A receiving flip-flop needs its input stable for a window around the active clock edge. Setup and hold checks describe opposite sides of that window and protect reliable state transfer through a synchronous circuit.

ASARK Semiconductor & VLSI guide · Timing overview

How data moves between flip-flops

A common synchronous path starts at a launch flip-flop, passes through combinational logic, and ends at a capture flip-flop. On a clock event, the launch flip-flop changes its output after a clock-to-Q delay, often written Tcq. The new value then propagates through gates and wires. The capture flip-flop samples its input at a later clock edge according to the design’s clock relationship.

The maximum data-path delay controls whether the new value arrives soon enough for the next capture edge. The minimum data-path delay controls whether it arrives too soon and disturbs the value that the capture register still needs to retain after its current edge. These become setup and hold checks respectively.

Clock skew is the difference in clock arrival time at the capture and launch registers. Define Tskew = capture-clock arrival − launch-clock arrival. Positive skew means the capture clock arrives later. For the simple same-frequency path described below, that later capture edge gives setup more time but makes hold more difficult. Actual clock-tree and multi-clock checks can have more complex relationships.

What is setup time?

Setup time, Tsetup, is the minimum interval that data must be stable before the active capture edge for the receiving flip-flop to meet its specified behaviour. A setup violation means the latest possible data arrival is too late relative to that edge. The captured value may be wrong or the flip-flop may take longer to resolve; design timing treats the path as failing rather than assuming a particular outcome.

What is hold time?

Hold time, Thold, is the minimum interval that data must remain stable after the active capture edge. A hold violation means the earliest new data can reach the capture input before that interval has elapsed, potentially overwriting the value being captured. It is a minimum-delay failure, not simply a lower maximum clock frequency problem.

Clock jitter describes variation in clock edge timing. Timing analysis reserves uncertainty to represent relevant jitter and modeling margin. Setup/hold values, clock-to-Q delay and cell delays depend on conditions such as process, voltage, temperature, slew and load. Static timing analysis checks those assumptions across specified modes and corners; see the STA guide.

Basic setup timing equation

For one register-to-register path with a capture edge one period after launch, a simplified setup condition is:

Tcq(max) + Tcomb(max) + Tsetup + Tuncertainty <= Tperiod + Tskew

Terms: Tcq(max) is maximum launch clock-to-Q delay; Tcomb(max) is maximum combinational and interconnect delay; Tsetup is capture-register setup requirement; Tuncertainty is the timing margin used for effects such as jitter; Tperiod is the interval between related clock edges; and Tskew is capture minus launch clock arrival as defined above. The expression assumes a simple single-cycle path, one related clock, and no additional source or network latency terms. Real STA uses explicit clock definitions, input/output delays, propagated or ideal clocks, derates and path-specific relationships.

Rearranging gives an approximate minimum period: Tperiod ≥ Tcq(max) + Tcomb(max) + Tsetup + Tuncertainty − Tskew. This helps explain why setup timing constrains maximum frequency: shortening the period reduces time available for the slowest data path. It is not a full signoff equation for every path.

Example 1: setup calculation

Assume a launch clock-to-Q maximum of 80 ps, combinational and wire maximum delay of 620 ps, capture setup requirement of 70 ps, uncertainty of 30 ps, and capture clock skew of +20 ps.

  1. Add the data and capture requirements: 80 + 620 + 70 + 30 = 800 ps.
  2. The path has a period plus skew available: Tperiod + 20 ps.
  3. Require Tperiod + 20 ≥ 800, so Tperiod ≥ 780 ps.
  4. Under only these simplified assumptions, the corresponding frequency ceiling is approximately 1 / 780 ps, or 1.28 GHz. Real design margins and other paths can require a slower clock.

These values are illustrative arithmetic, not a claim about a particular library or chip.

Basic hold timing equation

For a same-edge hold check in this simple register-to-register case, the earliest new data must not reach the capture input until its hold window ends:

Tcq(min) + Tcomb(min) >= Thold + Tskew + Tuncertainty

Tcq(min) is minimum clock-to-Q delay; Tcomb(min) is minimum logic and wire delay; Thold is the receiving register’s hold requirement; Tskew is capture minus launch clock arrival; and Tuncertainty represents the relevant margin. This pedagogical form assumes the same edge relationship and omits detailed clock latency, derating, CRPR and other tool-specific terms.

Example 2: hold calculation

Assume minimum clock-to-Q is 40 ps, minimum combinational and wire delay is 20 ps, hold requirement is 50 ps, capture skew is +15 ps and hold uncertainty is 10 ps.

  1. Earliest data arrival is 40 + 20 = 60 ps after the launch edge.
  2. The capture-side hold requirement is 50 + 15 + 10 = 75 ps after the launch edge.
  3. The path is short by 75 − 60 = 15 ps, so it has a 15 ps hold violation in this simplified model.

This is why setup and hold need separate analysis. A path can be fast enough for setup but too fast for hold, or slow enough for hold but too slow for setup.

How setup violations are addressed

Engineers first identify whether the path, constraints, clock relationship and operating mode are modeled correctly. If the failure is real, options can include reducing combinational depth, selecting faster cells where appropriate, improving placement and routing, reducing fanout or load, restructuring logic, changing the architecture, or adding a pipeline stage. A longer clock period can help if the product’s performance requirement allows it. Each change has side effects for area, power, latency and verification.

Retiming or pipelining changes where state boundaries sit and may change externally observed latency. It is therefore a functional design decision, not just a timing switch. Improving a report without preserving the specification is not a valid fix.

How hold violations are addressed

A common physical-design remedy is to add delay to a path that is too short, often by inserting buffers or choosing cells that increase minimum delay. Placement and routing adjustments can also change the path. The implementation tool must then recheck setup because added delay consumes some setup margin. Multiple corners and path groups are considered; fixing one hold path must not create another failure.

Changing the clock frequency alone does not generally repair a same-edge hold violation: the launch and capture edges for a hold check remain related to the same cycle edge. Clock-tree skew can influence hold and setup in opposite directions, so clock changes require coordinated analysis rather than a blanket rule. Read the path report to see launch/capture clock arrivals, cell and net delays, uncertainty and slack.